21.8.61 set_input

Description

Sets the input jitter for a given clock.

set_input_jitter <input_jitter> <clock>

Important:

This constraint is not supported as a Tcl command. Enter it as part of a timing constraint (.sdc) file.
The SynplifyPro synthesis software ignores the set_input_jitter SDC constraint.


Parameter	Type	Description
`<input_jitter>`	floating point	Specifies the input jitter value in nanoseconds. This value must be greater than zero. The input_jitter value allows the user to specify the clock jitter on the external clock. For RTG4™ FPGAs, the user must include the larger of the external clock jitter or the RTG4 Input Buffer jitter data sheet specifications using this constraint. Furthermore for RTG4 FPGAs, if the input port is a Strobe input to the RTG4 CCC SpaceWire clock and data recovery circuit, use this constraint to account for the CCC SpaceWire effective recovered clock jitter data sheet specification during STA.
`<input clock>`	string	Specifies the clock on which to apply the input clock jitter value. The user must ensure there is also a create_clock SDC constraint applied to the same clock input port to define that input as a clock for Static Timing Analysis (STA).

The following example sets the input jitter to 2.1 nanosecond.

Important: The clock used to set the jitter is the clock name that is defined in the create_clock command. CLK is the clock port name.

create_clock -name { clockName }-period 20 -waveform {0 10 } [ get_ports { CLK } ]
set_input_jitter 2.1 [ get_clocks { clockName } ]