21.8.6 create_clock

Description

Creates a clock constraint on the specified sources in the current design, or a virtual clock if no source other than a name is specified. It also defines its period and waveform. The static timing analysis tool uses this information to propagate the waveform across the clock network to the clock pins of all sequential elements driven by this clock source.

The clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

create_clock [ -name clock_name ] [-add] -period period_value \
[ -waveform edge_list ][ source_objects ]
Table 21-3. Arguments
ParameterTypeDescription
namestringSpecifies the name of the clock constraint. You must specify either a clock name or a source. If the -name option is not used, the clock name is specified as source name. The clock name refer to the clock in other commands. You can specify name as: -name {clk} or -name clk.
addNoneSpecifies that a new clock constraint is created at the same source port as the existing clock without overriding the existing constraint. The name of the new clock constraint with the -add option must be different than the existing clock constraint. Otherwise, it will override the existing constraint, even with the -add option. The -name option must be specified with the -add option.
periodrealSpecifies the clock period in nanoseconds. The value you specify is the minimum time over which the clock waveform repeats. The period_value must be greater than zero.
waveformrealSpecifies the rise and fall times of the clock waveform in ns over a complete clock period. There must be exactly two transitions in the list, a rising transition followed by a falling transition. So in the edge list, the falling edge value must be greater than the rising edge value. For example, a clock waveform of period 19 that has a rising edge at 3 ns and a falling edge at 8 ns will have the waveform defined as [ 3 8 ].
source_objectslist of stringSpecifies the source of the clock constraint. The source can be ports, pins, or nets in the design. If you specify a clock constraint on a pin that already has a clock, the new clock replaces the existing one. Specify either a source or a clock name.
Return TypeDescription
integerReturns the ID of the clock constraint.
Table 21-4. Error Codes
Error CodeDescription
Error: SDC0001Invalid clock constraint: clock source is incorrect.
Error: SDC0006Invalid clock constraint: clock period is incorrect for the specified clock.
Error: SDC0007Invalid clock constraint: waveform is incorrect.
Error: SDC0061Invalid clock constraint: Missing or Illegal parameter/value.
Error: SDC0069Invalid clock constraint: Need to specify clock name with -add option.

Supported Families

PolarFire®
PolarFire SoC
SmartFusion® 2
IGLOO® 2
RTG4™

Example

The following example creates two clocks, one on port CK1 with a period of 6, and the other on port CK2 with a period of 6, a rising edge at 0, and a falling edge at 3.

create_clock -name {my_user_clock} -period 6 CK1
create_clock -name {my_other_user_clock} –period 6 –waveform {0 3} {CK2}

The following example creates a clock on port CK3 with a period of 7, a rising edge at 2, and a falling edge at 4.

create_clock –period 7 –waveform {2 4} [get_ports {CK3}]
The following example creates a new clock constraint clk2, in addition to clk1, on the same source port clk1 without overriding it.
create_clock -name clk1 -period 10 -waveform {0 5} [get_ports clk1]
create_clock -name clk2 –add -period 20 -waveform {0 10} [get_ports clk1]
The following example does not add a new clock constraint, even with the -add option, but overrides the existing clock constraint because of the same clock names.
Note: To add a new clock constraint in addition to the existing clock constraint on the same source port, the clock names must be different.
create_clock -name clk1 -period 10 -waveform {0 5} [get_ports clk1]
create_clock -name clk1 -add -period 50 -waveform {0 25} [get_ports clk1]

The following example shows the SDC constraint that must be added for 050 devices, with max accuracy of 4% and 52 MHz (clock period 19.230 ns).

create_clock -name {OSC_0/I_RCOSC_25_50MHZ/CLKOUT} -period 19.230 [ get_pins {OSC_0/I_RCOSC_25_50MHZ/CLKOUT}]

Related Examples on GitHub