21.8.60 set_input_delay
(Ask a Question)Description
Creates an input delay on a port list by defining the arrival time of an input relative to a clock in the current scenario.
The set_input_delay command sets input path delays on input ports relative to a clock edge. This usually represents a combinational path delay from the clock pin of a register external to the current design. For in/out (bidirectional) ports, you can specify the path delays for both input and output modes. The tool adds input delay to path delay for paths starting at primary inputs.
A clock is a singleton that represents the name of a defined clock constraint. This can be:
- a single port name used as source for a clock constraint.
- a single pin name used as source for a clock constraint; for instance
reg1:CLK. This name can be hierarchical (for instance,toplevel/block1/reg2:CLK). - an object accessor that will refer to one clock:
[get_clocks {clk}].
- The behavior of the -add_delay option is identical to that of PrimeTime(TM).
- If, using the
-add_delaymechanism, multiple constraints are otherwise identical, except they specify different-maxor-minvalues- The surviving
-maxconstraint will be the maximum of the-maxvalues. - The surviving
-minconstraint will be the minimum of the-minvalues.
- The surviving
set_input_delay delay_value -clock clock_ref [–max] [–min] [–clock_fall] [-rise] [-fall] [-add_delay] \
input_listArguments
| Parameter | Type | Description |
|---|---|---|
delay_value | real | Specifies the arrival time in nanoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge. |
clock | string | Specifies the clock reference to which the specified input delay is related. This is a mandatory argument. |
max | None | Specifies that the delay_value refers to the longest path arriving at the specified input. If you do not specify -max or -min options, the tool assumes maximum and minimum input delays to be equal. |
min | None | Specifies that the delay_value refers to the shortest path arriving at the specified input. If you do not specify -max or -min options, the tool assumes maximum and minimum input delays to be equal. |
clock_fall | None | Specifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge. |
rise | None | Specifies that the delay is relative to a rising transition on the specified port(s). If -rise or -fall is not specified, then rising and falling delays are assumed to be equal. |
fall | None | Specifies that the delay is relative to a falling transition on the specified port(s). If -rise or -fall is not specified, then rising and falling delays are assumed to be equal. |
add_delay | None | Specifies that this input delay constraint should be added to an existing constraint on the
same port(s). The -add_delay option
capture
information on multiple paths with different clocks or clock edges
leading to the same input port(s). |
input_list | list of string | Provides a list of input ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}). |
| Return Type | Description |
|---|---|
integer | Returns the ID of the clock input delay constraint. |
Error Codes
| Error Code | Description |
|---|---|
| Error: SDC0004 | clk does not match any clock name or source. |
| Error: SDC0015 | port list [get_ports {CLK_0_D}] is incorrect. |
| Error: SDC0054 | Invalid IO delay constraint: the min delay is greater than max delay. |
| Error: SDC0061 | Parameter _AtclParam0_ has illegal value. |
Supported Families
| PolarFire® |
| PolarFire SoC |
| SmartFusion® 2 |
| IGLOO® 2 |
| RTG4™ |
Example
The following example sets an input delay of 1.2 ns for port data1 relative to the rising edge of
CLK1.
set_input_delay 1.2 -clock [get_clocks CLK1] [get_ports data1]The following example sets a different maximum and minimum input delay for port IN1 relative to the falling edge of CLK2.
set_input_delay 1.0 -clock_fall -clock CLK2 –min {IN1}set_input_delay 1.4 -clock_fall -clock CLK2 –max {IN1}The following example demonstrates an override condition of two constraints. The first constraint is overridden because the second constraint specifies a different clock for the same input.
set_input_delay 1.0 -clock CLK1 –max {IN1}set_input_delay 1.4 -clock CLK2 –max {IN1}The next example is almost the same as the previous one, however, in this case, the user has specified -add_delay, so both constraints will be honored.
set_input_delay 1.0 -clock CLK1 –max {IN1}set_input_delay 1.4 -add_delay -clock CLK2 –max {IN1}The following example is more complex:
- All constraints are for an input to port PAD1
relative to a rising edge clock
CLK2. Each combination of{-rise, -fall} x {-max, -min}generates an independent constraint. But the max rise delay of 5 and the max rise delay of 7 interfere with each other. - For a -max option, the maximum value overrides all lower values. Thus the first constraint will be overridden and the max rise delay of 7 will survive.
set_input_delay 5 -max -rise -add_delay [get_clocks CLK2] [get_ports PAD1] # will be overriddenset_input_delay 3 -min -fall -add_delay [get_clocks CLK2] [get_ports PAD1]set_input_delay 3 -max -fall -add_delay [get_clocks CLK2] [get_ports PAD1]set_input_delay 7 -max -rise -add_delay [get_clocks CLK2] [get_ports PAD1]