21.8.62 set_max_delay

Description

Specifies the required maximum delay for timing paths in the current design. The path length for any startpoint in from_list to any endpoint in to_list must be less than the delay_value. The timing engine automatically derives the individual maximum delay targets from clock waveforms and port input or output delays. For more information, refer to the create_clock, set_input_delay, and set_output_delay commands. The maximum delay constraint is a timing exception. This constraint overrides the default single cycle timing relationship for one or more timing paths. This constraint also overrides a multi-cycle path constraint.

You must specify at least one of the -from , -to, or -through arguments for this constraint to be valid.

set_max_delay delay_value [-ignore_clock_latency] [-from from_list ] [-to to_list ] [-through through_list ]

Arguments

ParameterTypeDescription
delay_valuefloating pointSpecifies a floating point number in nanoseconds that represents the required maximum delay value for specified paths.
  • If the path starting point is on a sequential device, the tool includes clock skew in the computed delay.
  • If the path starting point has an input delay specified, the tool adds that delay value to the path delay.
  • If the path ending point is on a sequential device, the tool includes clock skew and library setup time in the computed delay.
  • If the ending point has an output delay specified, the tool adds that delay to the path delay.
fromlist of stringsSpecifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.
tolist of stringsSpecifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.
throughlist of stringsSpecifies a list of pins, ports, nets, or instances (cells) through which the timing paths must pass.
ignore_clock_latencyflagSpecifies that the calculation of slack for the specified path excludes clock skew and jitter, and only the data path is considered.
Note:
  • The flag is useful for analyzing the paths between the sequential elements driven by asynchronous clocks.
  • This argument is not supported by the Synplify Pro Synthesis software. In Libero Design flow, this option is skipped for the Synplify Pro Synthesis software.
Return TypeDescription
integerReturns the ID of the clock maximum delay constraint.

Error Codes

Error CodeDescription
Error: SDC0021Invalid max delay constraint: the -from value is incorrect.
Error: SDC0022Invalid max delay constraint: the -from is empty.
Error: SDC0023Invalid max delay constraint: the -to value is incorrect.
Error: SDC0024Invalid max delay constraint: the -to is empty.
Error: SDC0026Invalid max delay constraint: the -through is empty
Error: SDC0061Invalid max delay constraint: Missing or Illegal parameter/value.
Warningcell (get_cells) is incorrect type;"-through" objects must be of type net (get_nets), or pin (get_pins).
Note: Constraint will be disabled.
Warningport (get_ports) is incorrect type;"-through" objects must be of type net (get_nets), or pin (get_pins).
Note: Constraint will be disabled.

Supported Families

PolarFire®
PolarFire SoC
SmartFusion® 2
IGLOO® 2
RTG4™

Example

The following example sets a maximum delay by constraining all paths from ff1a:CLK or ff1b:CLK to ff2e:D with a delay less than 5 ns.

set_max_delay 5 -from {ff1a:CLK ff1b:CLK} -to {ff2e:D}

The following example sets a maximum delay by constraining all paths to output ports whose names start by "out" with a delay less than 3.8 ns.

set_max_delay 3.8 -to [get_ports out*]

Related Examples on GitHub

See Also