21.8.7 create_generated_clock

Description

Creates a generated clock in the current design at a declared source by defining its frequency with respect to the frequency at the reference pin. The static timing analysis tool uses this information to compute and propagate its waveform across the clock network to the clock pins of all sequential elements driven by this source.

The generated clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

create_generated_clock [-name clock_name ] [–add] \
                       [-master_clock clock_name ] \
                       -source reference_pin \
                       [- divide_by divide_factor ] \
                       [-multiply_by multiply_factor ] \
                       [-invert] source [-edges values ] \
                       [-edge_shift values ]

Arguments

ParameterTypeDescription
namestringSpecifies the name of the clock constraint. If the -name option is not used, the generated clock receives the same name specified in the source. The clock name refer to the clock in other commands. You can specify -name {my_gen_clk} or -name my_gen_clk.
addNoneSpecifies that the generated clock constraint is a new clock constraint in addition to the existing one at the same source. Use this option to capture the case where multiple generated clocks must be specified on the same source, because multiple clocks fan into the master pin. If you specify this option, you must also use the -name option. The name of the clock constraint should be different from the existing clock constraint. With this option, the -master_clock and -name options must be specified.
master_clockstringSpecifies the master clock used for the generated clock when multiple clocks fan into the master pin. This option must be used in conjunction with -add option of the generated clock.
Note:
  1. The master_clock option is used only with the -add option for the generated clocks.
  2. If there are multiple master clocks fanning into the same reference pin, the first generated clock specified uses the first master clock as its source clock.
  3. The subsequent generated clocks specified with the -add option can choose any of the master clocks as their source clock (including the first master clock specified).
sourcestringSpecifies the reference pin in the design from which the clock waveform is to be derived. You must specify the -source reference pin.
divide_byintegerSpecifies the frequency division factor. This option cannot be used with -egde list. If -egde is specified, the divide_by value defaults to one. For example, if the divide_factor is equal to 2, the generated clock period is twice the reference clock period. If you set the divide_by value to 1.2 or 4/2 or 8a2, it is being truncated as 1 or 4 or 8, and no warning is reported.
multiply_byintegerSpecifies the frequency multiplication factor. This option cannot be used with -egde list. If egde is specified, the multiply_by and divide_by values default to one. For example, if the multiply_factor is equal to 2, the generated clock period is half the reference clock period. If you set the multiply_by value to 1.2 or 4/2 or 8a2, it is being truncated as 1 or 4 or 8, and no warning is reported.
invertNoneSpecifies that the generated clock waveform is inverted with respect to the reference clock.
sourcelist of stringsSpecifies the source of the clock constraint on internal pins of the design. If you specify a clock constraint on a pin that already has a clock, the new clock replaces the existing clock. Only one source is accepted. Wildcards are accepted as long as the resolution shows one pin. You must specify a source.
edgeslist of integersSpecifies a list of positive integers which represent the edges from the source clock that are to form the edges of the generated clock. To generate the clock, three values must be specified. If you specify less than three values, a tool tip indicates an error. This option cannot be used with the -divide_by/-multiply_by factor.
edge_shiftlist of floating point numbersSpecifies a list of three floating point numbers which represent the amount of shift (in nanoseconds) that the specified edges are to undergo to yield the final generated clock waveform. These floating point values can be positive or negative. Positive value indicates a shift later in time, while negative indicates a shift earlier in time. With this option, the -edges option must be specified.
Return TypeDescription
integerReturns the ID of the generated clock constraint.

Error Codes

Error CodeDescription
Error: SDC0004Invalid generated clock constraint: Name does not match any clock name or source.
Error: SDC0015Invalid generated clock constraint: Port list is incorrect.
Error: SDC0016Invalid generated clock constraint: Port list is empty.
Error: SDC0061Invalid generated clock constraint: The -edges argument is empty invoked from within command.
Error: SDC0062Invalid generated clock constraint: The -edges list size must be three.
Error: SDC0063Invalid generated clock constraint: The -edges list elements are not in increasing order.
Error: SDC0065Invalid generated clock constraint: The -edges cannot be used with the -multiply_by or -divide_by option.
Error: SDC0066Invalid generated clock constraint: The -edge_shift does not have accompanying -edges.
Error: SDC0069Invalid clock constraint: Need to specify a clock name with the -add option.

Supported Families

PolarFire®
PolarFire SoC
SmartFusion® 2
IGLOO® 2
RTG4™

Example

The following example creates a generated clock on pin U1/reg1:Q with a period twice as long as the period at the reference port CLK.

create_generated_clock -name {my_user_clock} -divide_by 2 \
                       -source [get_ports {CLK}] U1/reg1:Q

The following example creates a generated clock at the primary output of myPLL with a period 3⁄4 of the period at the reference pin clk.

create_generated_clock -divide_by 3 -multiply_by 4 \
                       -source clk [get_pins {myPLL:CLK1}]

The following example creates a new generated clock gen2 in addition to gen1 derived from same master clock as the existing generated clock, and the new constraint is added to pin r1/CLK.

create_generated_clock -name gen1 -multiply_by 1 \
                       -source [get_ports clk1] [get_pins r1/CLK]
create_generated_clock -name gen2 -add -master_clock clk1 \
                       -source [get_ports clk1] \
                       -multiply_by 2 [get_pins r1/CLK]

The following example does not create a new generated clock constraint in addition to the existing clock, but overrides even with the -add option enabled because the same names are used.

create_generated_clock -name gen2 -source [get_ports clk1] \
                       -multiply_by 3 [get_pins r1/CLK]
create_generated_clock -name gen2 -source [get_ports clk1] \
                       -multiply_by 4 -master_clock clk1 \
                       -add [get_pins r1/CLK]

The following example shows an SDC constraint for a generated clock of 50 MHz reference clock and 100 MHz output clock with a 90° phase shift.

create_generated_clock \
          -name {FCCC_0/GL0} -multiply_by 4 -divide_by 2 \                                             
          -source [get_pins {FCCC_0/CCC_INST/RCOSC_25_50MHZ}] \
          -phase 0 [get_pins {FCCC_0/CCC_INST/GL0}]
create_generated_clock \
          -name {FCCC_0/GL1} -multiply_by 4 -divide_by 2 \
          -source [get_pins {FCCC_0/CCC_INST/RCOSC_25_50MHZ}] \
          -phase 90 [get_pins {FCCC_0/CCC_INST/GL1}]
The following example uses the -pll_feedback and the -pll_output switches with the create_generated_clock constraint when the CCC/PLL is used in the external feedback mode.
Important: The following example is supported by PolarFire and RTG4 devices.
create_clock -period 25.000 
-waveform {0.000 12.500} 
-name {sys_clk} [get_ports \{clk}] 

create_generated_clock 
-name {PLL_200MHZ} 
-multiply_by 5 
-source [ get_pins { phase_locked_loop0/pll_pf_40in_40_100_200out_0/pll_inst_0/REF_CLK_0 } ] 
-pll_output [ get_pins { phase_locked_loop0/pll_pf_40in_40_100_200out_0/pll_inst_0/OUT0 } ] 
-pll_feedback [ get_pins { phase_locked_loop0/pll_pf_40in_40_100_200out_0/pll_inst_0/FB_CLK } ] 
-phase 0 [ get_pins { phase_locked_loop0/pll_pf_40in_40_100_200out_0/pll_inst_0/OUT0 } ]

See Also

Related Examples on GitHub