21.8.52 set_clock

Description

Defines the delay between an external clock source and the definition pin of a clock within SmartTime.

Clock source latency defines the delay between an external clock source and the definition pin of a clock within SmartTime. You can specify both an "early" delay and a "late" delay for this latency, providing an uncertainty which SmartTime propagates through its calculations. Rising and falling edges of the same clock can have different latencies. If only one value is provided for the clock source latency, it is taken as the exact latency value, for both rising and falling edges.

Clock latency is of two types:

External latency (source) - From an external source to on-chip clock definition point using the -source argument.
Internal latency (network) - From a clock generator to an end point (FF) due to clock tree synthesis (CTS).

In FPGA, internal clock latency is not used because the clock tree is already inserted and Libero SoC tool is already aware of the delay. Hence, set_clock_latency is primarily used to model external latency in FPGA.

When external clock latency is modeled using the -source arguments, hold calculations are never impacted because the hold checks occur for the same clock edge. Setup times are only impacted when the -early and -late arguments are used because otherwise the clock is uniformly delayed to all endpoints in the design. The following table summarizes the behavior:


`-source` used	`-early` used	`-late` used	Result
Yes	No	No	No setup or hold impact
Yes	No	Yes	No setup or hold impact
Yes	Yes	No	No setup or hold impact
Yes	Yes	Yes	Setup check only
No	N/A	N/A	Not recommended for FPGA designs.

Setup time is calculated for a scenario where the launch edge is delayed and the capture edge is early:

The -early value is added from the required time.
The -late value is added to the arrival time

set_clock_latency -source [-rise] [-fall] [-early] [-late] delay clock

Arguments


Parameter	Type	Description
`source`	None	Specifies the source latency on a clock pin, potentially only on certain edges of the clock.
`rise`	None	Specifies the edge for which this constraint will apply. If neither or both rise and fall are passed, the same latency is applied to both edges.
`fall`	None	Specifies the edge for which this constraint will apply. If neither or both fall and rise are passed, the same latency is applied to both edges.
`late`	None	Optional. Specifies that the latency is late bound on the latency. The appropriate bound provide the most pessimistic timing scenario. However, if the value of `-late` is less than the value of `-early`, optimistic timing takes place which could result in incorrect analysis. If neither or both `-early` and `-late` are provided, the same latency is used for both bounds, which results in the latency having no effect for single clock domain setup and hold checks.
`early`	None	Optional. Specifies that the latency is early bound on the latency. The appropriate bound provide the most pessimistic timing scenario. However, if the value of `-late` is less than the value of `-early`, optimistic timing takes place which could result in incorrect analysis. If neither or both `-early` and `-late` are provided, the same latency is used for both bounds, which results in the latency having no effect for single clock domain setup and hold checks.
`delay`	floating point	Specifies the latency value for the constraint.
`clock`	string	Specifies the clock to which the constraint is applied. This clock must be constrained.

Error Codes


Error Code	Description
Error: SDC0061	Invalid clock latency constraint: Parameter has illegal value invoked from within command.

Supported Families


PolarFire®
PolarFire SoC
SmartFusion® 2
IGLOO® 2
RTG4™

Example

The following example sets an early clock source latency of 0.4 on the rising edge of main_clock. It also sets a clock source latency of 1.2, for both the early and late values of the falling edge of main_clock. The late value for the clock source latency for the falling edge of main_clock remains undefined.

set_clock_latency –source –rise –early 0.4 { main_clock }

set_clock_latency –source –fall 1.2 { main_clock }

Related Examples on GitHub

set_clock_latency

v2024.2

21.8.52 set_clock_latency