44.4.1.21 USB Endpoint Control 0 Register
| Name: | UEP0 |
| Offset: | 0x4300 |
| Reset: | 0x0 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LSPD | RETRYDIS | EPCONDIS | EPRXEN | EPTXEN | EPSTALL | EPHSHK | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – LSPD Low-Speed Direct Connection Enable bit (Host mode)
| Value | Description |
|---|---|
| 1 | Direct connection to a low-speed device is enabled |
| 0 | Direct connection to a low-speed device is disabled; hub required with PRE_PID |
Bit 6 – RETRYDIS Retry Disable bit (Host mode)
| Value | Description |
|---|---|
| 1 | Retry NAK’d transactions are disabled |
| 0 | Retry NAK’d transactions are enabled; retry done in hardware |
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
If EPTXEN = 1 and EPRXEN=1:
| Value | Description |
|---|---|
| 1 | Disable endpoint 0 for control transfers; only TX and RX transfers are allowed |
| 0 | Enable endpoint 0 for control (SETUP) transfers; TX and RX transfers are also allowed |
Bit 3 – EPRXEN Endpoint Receive Enable bit
| Value | Description |
|---|---|
| 1 | Endpoint 0 receive is enabled |
| 0 | Endpoint 0 receive is disabled |
Bit 2 – EPTXEN Endpoint Transmit Enable bit
| Value | Description |
|---|---|
| 1 | Endpoint 0 transmit is enabled |
| 0 | Endpoint 0 transmit is disabled |
Bit 1 – EPSTALL Endpoint Stall Status bit
| Value | Description |
|---|---|
| 1 | Endpoint 0 is stalled |
| 0 | Endpoint 0 is not stalled |
Bit 0 – EPHSHK Endpoint Handshake Enable bit
| Value | Description |
|---|---|
| 1 | Endpoint handshake is enabled |
| 0 | Endpoint handshake is disabled (typically used for isochronous endpoints) |