44.4.1.6 USB Interrupt Register
-
This bit is valid only if the HOSTEN bit is set (see UCON register), there is no activity on the USB for 2.5 μs, and the current bus state is not SE0.
- When not in Suspend mode, this interrupt should be disabled.
- Clearing this bit will cause the STAT FIFO to advance.
- Only error conditions enabled through the UEIE register will set this bit.
| Name: | UIR |
| Offset: | 0x4200 |
| Reset: | 0x0 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STALLIF | ATTACHIF | RESUMEIF | IDLEIF | TRNIF | SOFIF | UERRIF | URSTIF/DETACHIF | ||
| Access | R/K | R/K | R/K | R/K | R/K | R/K | R/K | R/K | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – STALLIF STALL Handshake Interrupt bit
Write a ‘1’ to this bit to clear the interrupt.
| Value | Description |
|---|---|
| 1 | In Host mode, a STALL handshake was received during the handshake phase of the transaction. In Device mode, a STALL handshake was transmitted during the handshake phase of the transaction. |
| 0 | STALL handshake has not been sent |
Bit 6 – ATTACHIF Peripheral Attach Interrupt bit(1)
Write a ‘1’ to this bit to clear the interrupt.
| Value | Description |
|---|---|
| 1 | Peripheral attachment was detected by the USB OTG module |
| 0 | Peripheral attachment was not detected |
Bit 5 – RESUMEIF Resume Interrupt bit(2)
Write a ‘1’ to this bit to clear the interrupt.
| Value | Description |
|---|---|
| 1 | K-State is observed on the D+ or D- pin for 2.5 μs |
| 0 | K-State is not observed |
Bit 4 – IDLEIF Idle Detect Interrupt bit
Write a ‘1’ to this bit to clear the interrupt.
| Value | Description |
|---|---|
| 1 | Idle condition is detected (constant Idle state of 3 ms or more) |
| 0 | No Idle condition is detected |
Bit 3 – TRNIF Token Processing Complete Interrupt bit(3)
Write a ‘1’ to this bit to clear the interrupt.
| Value | Description |
|---|---|
| 1 | Processing of current token is complete; a read of the USTAT register provides endpoint information |
| 0 | Processing of current token is not complete |
Bit 2 – SOFIF SOF Token Interrupt bit
Write a ‘1’ to this bit to clear the interrupt.
| Value | Description |
|---|---|
| 1 | SOF token received by the peripheral or the SOF threshold reached by the host |
| 0 | SOF token was not received nor threshold reached |
Bit 1 – UERRIF USB Error Condition Interrupt bit(4)
Write a ‘1’ to this bit to clear the interrupt.
| Value | Description |
|---|---|
| 1 | Unmasked Error condition has occurred |
| 0 | Unmasked Error condition has not occurred |
Bit 0 – URSTIF/DETACHIF URSTIF: USB Reset Interrupt bit (Device mode) DETACHIF: USB Detach Interrupt bit (Host mode)
Write a ‘1’ to this bit to clear the interrupt.
| Value | Description |
|---|---|
| 1 |
URSTIF: Valid USB Reset has occurred DETACHIF: Peripheral detachment was detected by the USB OTG module |
| 0 |
URSTIF: No USB Reset has occurred DETACHIF: Peripheral detachment was not detected |