44.4.1.5 USB Power Control Register
| Name: | UPWRC |
| Offset: | 0x4080 |
| Reset: | 0x0 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UACTPND | USLPGRD | USBBUSY | USUSPEND | USBPWR | |||||
| Access | HS | R/W | R/W | R/W | R/K | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – UACTPND USB Activity Pending bit
| Value | Description |
|---|---|
| 1 | USB bus activity has been detected; but an interrupt is pending, it has not been generated yet |
| 0 | An interrupt is not pending |
Bit 4 – USLPGRD USB Sleep Entry Guard bit
| Value | Description |
|---|---|
| 1 | Sleep entry is blocked if USB bus activity is detected or if a notification is pending |
| 0 | USB OTG module does not block Sleep entry |
Bit 3 – USBBUSY USB OTG module Busy bit
Note: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid
and writes to all USB OTG module registers produce undefined results.
| Value | Description |
|---|---|
| 1 | USB OTG module is active or disabled, but not ready to be enabled |
| 0 | USB OTG module is not active and is ready to be enabled |
Bit 1 – USUSPEND USB Suspend Mode bit
| Value | Description |
|---|---|
| 1 |
USB OTG module is placed in Suspend mode (The 48 MHz USB clock is gated off. The transceiver is placed in a low-power state.) |
| 0 | USB OTG module operates normally |
Bit 0 – USBPWR USB Operation Enable bit
Write a ‘1’ to this bit to clear the interrupt.
| Value | Description |
|---|---|
| 1 | USB OTG module is turned on |
| 0 | USB OTG module is disabled. Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power consumption. |