44.4.1.22 USB Endpoint Control n Register (n=1...15)
| Name: | UEPn |
| Offset: | 0x4310 + (n-1)*0x10 [n=1..15] |
| Reset: | 0x0 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EPCONDIS | EPRXEN | EPTXEN | EPSTALL | EPHSHK | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
If EPTXEN = 1 and EPRXEN=1:
| Value | Description |
|---|---|
| 1 | Disable endpoint n for control transfers; only TX and RX transfers are allowed |
| 0 | Enable endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed |
Bit 3 – EPRXEN Endpoint Receive Enable bit
| Value | Description |
|---|---|
| 1 | Endpoint n receive is enabled |
| 0 | Endpoint n receive is disabled |
Bit 2 – EPTXEN Endpoint Transmit Enable bit
| Value | Description |
|---|---|
| 1 | Endpoint n transmit is enabled |
| 0 | Endpoint n transmit is disabled |
Bit 1 – EPSTALL Endpoint Stall Status bit
| Value | Description |
|---|---|
| 1 | Endpoint n is stalled |
| 0 | Endpoint n is not stalled |
Bit 0 – EPHSHK Endpoint Handshake Enable bit
| Value | Description |
|---|---|
| 1 | Endpoint handshake is enabled |
| 0 | Endpoint handshake is disabled (typically used for isochronous endpoints) |