38.7.10 USBHS Device Global Interrupt Disable Register
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clears the corresponding bit in USBHS_DEVIMR. |
| Name: | USBHS_DEVIDR |
| Offset: | 0x0014 |
| Reset: | - |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DMA_7 | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PEP_9 | PEP_8 | PEP_7 | PEP_6 | PEP_5 | PEP_4 | ||||
| Access | W | W | W | W | W | W | |||
| Reset | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PEP_3 | PEP_2 | PEP_1 | PEP_0 | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UPRSMEC | EORSMEC | WAKEUPEC | EORSTEC | SOFEC | MSOFEC | SUSPEC | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |