38.7.17 USBHS Device Endpoint Interrupt Clear n Register (Control, Bulk, Interrupt Endpoints)
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in the ”Device Endpoint n Configuration Register”.
For additional information, see ”Device Endpoint n Status Register (Control, Bulk, Interrupt Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVEPTISRn.
| Name: | USBHS_DEVEPTICRn |
| Offset: | 0x0160 + n*0x04 [n=0..9] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHORTPACKETC | STALLEDIC | OVERFIC | NAKINIC | NAKOUTIC | RXSTPIC | RXOUTIC | TXINIC | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |