38.7.5 USBHS Device General Control Register

Name: USBHS_DEVCTRL
Offset: 0x0000
Reset: 0x00000100
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        OPMODE2 
Access R/W 
Reset 0 
Bit 15141312111098 
 TSTPCKTTSTKTSTJLSSPDCONF[1:0]RMWKUPDETACH 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000001 
Bit 76543210 
 ADDENUADD[6:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 16 – OPMODE2 Specific Operational Mode

ValueDescription
0

The UTMI transceiver is in normal operating mode.

1

The UTMI transceiver is in the Disable bit stuffing and NRZI encoding operational mode for test purposes.

Bit 15 – TSTPCKT Test Packet Mode

ValueDescription
0

The UTMI transceiver is in normal operating mode.

1

The UTMI transceiver generates test packets for test purposes.

Bit 14 – TSTK Test Mode K

ValueDescription
0

The UTMI transceiver is in normal operating mode.

1

The UTMI transceiver generates high-speed K state for test purposes.

Bit 13 – TSTJ Test Mode J

ValueDescription
0

The UTMI transceiver is in normal operating mode.

1

The UTMI transceiver generates high-speed J state for test purposes.

Bit 12 – LS Low-Speed Mode Force

This bit can be written even if USBHS_CTRL.USBE = 0 or USBHS_CTRL.FRZCLK = 1. Disabling the USBHS (by writing a zero to the USBHS_CTRL.USBE bit) does not reset this bit.

ValueDescription
0

The full-speed mode is active.

1

The low-speed mode is active.

Bits 11:10 – SPDCONF[1:0] Mode Configuration

This field contains the peripheral speed:

ValueNameDescription
0 NORMAL

The peripheral starts in full-speed mode and performs a high-speed reset to switch to high-speed mode if the host is high-speed-capable.

1 LOW_POWER

For a better consumption, if high speed is not needed.

2 HIGH_SPEED

Forced high speed.

3 FORCED_FS

The peripheral remains in full-speed mode whatever the host speed capability.

Bit 9 – RMWKUP Remote Wakeup

This bit is cleared when the USBHS receives a USB reset or once the upstream resume has been sent.

ValueDescription
0

No effect.

1

Sends an upstream resume to the host for a remote wakeup.

Bit 8 – DETACH Detach

Note: When operating in high-speed mode, ensure that the device detach (USBHS_DEVCTRL_DETACH = 1) is followed by a USB module disable (USBHS_CTRL.USBE = 0). To re-attach the device, enable the USB module ((USBHS_CTRL.USBE = 1) and then clear the detach bit (USBHS_DEVCTRL_DETACH = 0).
ValueDescription
0

Reconnects the device.

1

Physically detaches the device (disconnects the internal pull-up resistor from D+ and D-).

Bit 7 – ADDEN Address Enable

This bit is cleared when a USB reset is received.

ValueDescription
0

No effect.

1

Activates the UADD field (USB address).

Bits 6:0 – UADD[6:0] USB Address

This field contains the device address.

This field is cleared when a USB reset is received.