38.7.9 USBHS Device Global Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

ValueDescription
0The corresponding interrupt is not enabled.
1The corresponding interrupt is enabled.
Name: USBHS_DEVIMR
Offset: 0x0010
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 DMA_7DMA_6DMA_5DMA_4DMA_3DMA_2DMA_1  
Access RRRRRRR 
Reset 0000000 
Bit 2322212019181716 
   PEP_9PEP_8PEP_7PEP_6PEP_5PEP_4 
Access RRRRRR 
Reset 000000 
Bit 15141312111098 
 PEP_3PEP_2PEP_1PEP_0     
Access RRRR 
Reset 0000 
Bit 76543210 
  UPRSMEEORSMEWAKEUPEEORSTESOFEMSOFESUSPE 
Access RRRRRRR 
Reset 0000000 

Bits 25, 26, 27, 28, 29, 30, 31 – DMA_x DMA Channel x Interrupt Mask

Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PEP_x Endpoint x Interrupt Mask

Bit 6 – UPRSME Upstream Resume Interrupt Mask

Bit 5 – EORSME End of Resume Interrupt Mask

Bit 4 – WAKEUPE Wakeup Interrupt Mask

Bit 3 – EORSTE End of Reset Interrupt Mask

Bit 2 – SOFE Start of Frame Interrupt Mask

Bit 1 – MSOFE Micro Start of Frame Interrupt Mask

Bit 0 – SUSPE Suspend Interrupt Mask