3.4.4.12.2 Interrupt Vector Fetch

Interrupt vector fetches are not cached. The vector fetch will occur as soon as the current program memory fetch in progress (if any) has been completed.

The ISB is effectively bypassed for a vector fetch, and the fetch address is forwarded to the program memory directly. The contents of all ISB slices are preserved during the fetch, and no re-assignment to a new ISB slice occurs. A single program memory word is fetched during the vector fetch, and no predictive prefetching is performed as part of the vector fetch.

After the vector fetch has been completed, program execution will continue and appear as a program flow change as the CPU presents the previously fetched vector address. It is also possible that an interrupt occurred which is of higher priority. In this case, a new vector fetch address will be presented to the PBU.