3.4.4.13.1 Cache Coherency After Flash Write Events

The PBU has information on what Flash data were programmed or erased. Therefore, the PBU will monitor the appropriate signals from the NVM Controller and invalidate all cache and ISB buffers. Specifically, the NVM Controller provides a signal that is pulsed whenever the NVMCON.WR bit has been set and the corresponding Flash write addresses a panel that is currently being read to supply instructions to the CPU (Active panel in dual panel devices). This indicates that a Flash write sequence was initiated, after which the PBU should no longer expect Flash contents to match cached values in the PBU.

Automatic coherency control is optional for the PBU. If CHECON.CHECOH = 1 (default) and the NVM Controller pulses, all Instruction Cache lines and all ISB lines that are currently marked as valid will be invalidated. Any subsequent fetches from the CPU instruction bus should be fetched directly from Flash memory. If CHECON.CHECOH = 0, automatic coherency control will not occur.