3.4.4.4.1 ISB Buffers

The ISB provides one or more prefetch buffers (Slices) for Flash program memory. Each ISB requires two storage locations - one for the CPU/Cache to use, and another to allow a prefetch of the next Flash word. Each ISB buffer has address registers, status tracking registers and a FIFO buffer. The FIFO buffer is 129 bits wide. Of the 129 bits, 128 are used to hold the program data word read from memory. The remaining bits are used to indicate the data error status that occurred when reading from the external program memory.

The PBU is configured to have an ISB buffer depth of two. The A two-word depth allows the ISB to prefetch a second word while the first word is used by the CPU.

Each entry of an ISB buffer also includes an internal valid status (data valid) bit to determine whether the FIFO has usable data. This is necessary to ensure a buffer value cannot be used unless previously loaded. Conversely, if a data value is prefetched from Flash but subsequently not required by the CPU, it will not be stored in the target ISB buffer, which will remain unchanged.

The PBU ISB is configured for four slices.

Each slice includes an address valid bit. This bit is cleared upon Reset entry or whenever the slice is initialized and set when the ISB slice addresses are loaded. This functionality ensures that only valid addresses are ever present in the address registers (to prevent a false hit out of Reset).

Each line of the ISB includes an internal Data Valid bit to ensure a line cannot be used unless previously loaded. The state of this bit ultimately drives the data ready signal to the CPU to indicate when valid data is being presented on the instruction data bus. The Data Valid bit is also used to invalidate an ISB line in the event of a context change.

In some scenarios, like the execution of speculative instructions, a fetch may be started by the CPU but will later be abandoned. In such cases, the ISB asserts an internal Discard Prefetch flag to prevent the prefetch from being stored when the data is not needed by the CPU, thereby freeing up that ISB slice for subsequent use.