3.4.4.4.2 ISB HIT and LRU Logic

Each ISB buffer slice can have multiple lines of program memory, but only the top word of the FIFO is visible at any given time. An internal address tag register associated with each buffer slice indicates the address of the top word. Only this address is used to determine an ISB “hit” or “miss.” If the desired program word address is available in a deeper location of the FIFO, it will not be detected by the hit logic.

As each program word is consumed from an ISB buffer, the address tag register is incremented to point to the next 128-bit program word. This new address will then be used for subsequent address hit comparisons. Therefore, linear program flow will naturally result in a series of ISB hits as a complete program word is fully consumed, and then the FIFO address is incremented to point to the next program word that was prefetched.

If a program flow change occurs and a cache miss results, the address tag associated with each ISB slice must be considered to determine an ISB hit. If one of the ISB address tags matches, the requested program data will be sourced from the ISB slice that had the address tag match (hit).

The new ISB slice will continue to be used until the program flow changes again. If a program flow change occurs along with a cache miss and an ISB miss, the ISB employs a least recently used algorithm utilizing the LRU status bits associated with each buffer slice to determine which ISB buffer slice will be used for the new flow. A new program memory fetch will be started by the newly selected ISB slice to get the requested data.