25.6.4 Peripheral Module Disable 3 Control Register
Note:
- When a peripheral is disabled (PMD
=
1), its clocks are gated off and its Reset is asserted, providing a reduced power consumption. - Since the Reset to the peripheral
is asserted when PMD =
1, the module’s registers must be reinitialized to their desired values whenever the corresponding PMD bit is cleared.
| Name: | PMD3(1,2) |
| Offset: | 0xFA8 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCMD | U3MD | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 7 – CRCMD CRC Module Disable bit
| Value | Description |
|---|---|
| 1 | CRC module is disabled. |
| 0 | CRC module is enabled. |
Bit 3 – U3MD UART3 Module Disable bit
| Value | Description |
|---|---|
| 1 | UART3 module is disabled. |
| 0 | UART3 module is enabled. |