25.6.3 Peripheral Module Disable 2 Control Register
Note:
- When a peripheral is disabled (PMD =
1), its clocks are gated off and its Reset is asserted, providing a reduced power consumption. - Since the Reset to the peripheral is asserted when PMD =
1, the module’s registers must be reinitialized to their desired values whenever the corresponding PMD bit is cleared.
| Name: | PMD2(1,2) |
| Offset: | 0xFA6 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCP4MD | CCP3MD | CCP2MD | CCP1MD | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – CCP4MD SCCP4 Module Disable bit
| Value | Description |
|---|---|
| 1 | SCCP4 module is disabled. |
| 0 | SCCP4 module is enabled. |
Bit 2 – CCP3MD SCCP3 Module Disable bit
| Value | Description |
|---|---|
| 1 | SCCP3 module is disabled. |
| 0 | SCCP3 module is enabled. |
Bit 1 – CCP2MD SCCP2 Module Disable bit
| Value | Description |
|---|---|
| 1 | SCCP2 module is disabled. |
| 0 | SCCP2 module is enabled. |
Bit 0 – CCP1MD SCCP1 Module Disable bit
| Value | Description |
|---|---|
| 1 | SCCP1 module is disabled. |
| 0 | SCCP1 module is enabled. |