25.6.2 Peripheral Module Disable 1 Control Register
Note:
- When a peripheral is disabled (PMD
=
1), its clocks are gated off and its Reset is asserted, providing a reduced power consumption. - Since the Reset to the peripheral is asserted when PMD =
1, the module’s registers must be reinitialized to their desired values whenever the corresponding PMD bit is cleared.
| Name: | PMD1(1,2) |
| Offset: | 0xFA4 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| T1MD | PWMMD | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| I2C1MD | U2MD | U1MD | SPI2MD | SPI1MD | C1MD | ADC1MD | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 11 – T1MD Timer1 Module Disable bit
| Value | Description |
|---|---|
| 1 | Timer1 module is disabled. |
| 0 | Timer1 module is enabled. |
Bit 9 – PWMMD PWM Module Disable bit
| Value | Description |
|---|---|
| 1 | PWM module is disabled. |
| 0 | PWM module is enabled. |
Bit 7 – I2C1MD I2C1 Module Disable bit
| Value | Description |
|---|---|
| 1 | I2C1 module is disabled. |
| 0 | I2C1 module is enabled. |
Bit 6 – U2MD UART2 Module Disable bit
| Value | Description |
|---|---|
| 1 | UART2 module is disabled. |
| 0 |
UART2 module is enabled. |
Bit 5 – U1MD UART1 Module Disable bit
| Value | Description |
|---|---|
| 1 | UART1 module is disabled. |
| 0 | UART1 module is enabled. |
Bit 4 – SPI2MD SPI2 Module Disable bit
| Value | Description |
|---|---|
| 1 |
SPI2 module is disabled. |
| 0 |
SPI2 module is enabled. |
Bit 3 – SPI1MD SPI1 Module Disable bit
| Value | Description |
|---|---|
| 1 | SPI1 module is disabled. |
| 0 | SPI1 module is enabled. |
Bit 1 – C1MD CAN1 Module Disable bit
| Value | Description |
|---|---|
| 1 | CAN1 module is disabled. |
| 0 | CAN1 module is enabled. |
Bit 0 – ADC1MD ADC Module Disable bit
| Value | Description |
|---|---|
| 1 | ADC module is disabled. |
| 0 | ADC module is enabled. |