25.6.6 Peripheral Module Disable 6 Control Register

Note:
  1. When a peripheral is disabled (PMD = 1), its clocks are gated off and its Reset is asserted, providing a reduced power consumption.
  2. Since the Reset to the peripheral is asserted when PMD = 1, the module’s registers must be reinitialized to their desired values whenever the corresponding PMD bit is cleared.
Name: PMD6(1,2)
Offset: 0xFAE

Bit 15141312111098 
     DMA3MDDMA2MDDMA1MDDMA0MD 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
          
Access  
Reset  

Bit 11 – DMA3MD DMA3 Module Disable bit

ValueDescription
1

DMA3 module is disabled.
0

DMA3 module is enabled.

Bit 10 – DMA2MD DMA2 Module Disable bit

ValueDescription
1

DMA2 module is disabled.
0

DMA2 module is enabled.

Bit 9 – DMA1MD DMA1 Module Disable bit

ValueDescription
1

DMA1 module is disabled.
0

DMA1 module is enabled.

Bit 8 – DMA0MD DMA0 Module Disable bit

ValueDescription
1

DMA0 module is disabled.
0

DMA0 module is enabled.