14.4.8 DACx Slope Control Low Register

Name:	SLPxCONL
Offset:	0xC90, 0xCA0


Bit	15	14	13	12	11	10	9	8
	HCFSEL[3:0]				SLPSTOPA[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SLPSTOPB[3:0]				SLPSTRT[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:12 – HCFSEL[3:0] Hysteretic Comparator Function Input Select bits

The selected input signal controls the switching between the DACx high limit (DACxDATH) and the DACx low limit (DACxDATL) as the data source for the PDM DAC. It modifies the polarity of the comparator, and the rising and falling edges initiate the start of the LEB counter (TMCB[9:0] bits in DACxCONH).


Input Selection	Source
`1111`	`1`
`1110-0101`	`0`
`0100`	PWM4H
`0011`	PWM3H
`0010`	PWM2H
`0001`	PWM1H
`0000`	`0`

Bits 11:8 – SLPSTOPA[3:0] Slope Stop A Signal Select bits

The selected Slope Stop A signal is logically OR’d with the selected Slope Stop B signal to terminate the slope function.


Slope Stop A Signal Selection	Source
`1111`	`1`
`1110-0101`	`0`
`0100`	PWM4 Trigger 2
`0011`	PWM3 Trigger 2
`0010`	PWM2 Trigger 2
`0001`	PWM1 Trigger 2
`0000`	`0`

Bits 7:4 – SLPSTOPB[3:0] Slope Stop B Signal Select bits

The selected Slope Stop B signal is logically OR’d with the selected Slope Stop A signal to terminate the slope function.


Slope Stop B Signal Selection	Source
`1111`	`1`
`1110-0010`	`0`
`0001`	CMP1 out
`0000`	`0`

Bits 3:0 – SLPSTRT[3:0] Slope Start Signal Select bits


Slope Start Signal Selection	Source
`1111`	`1`
`1110-0101`	`0`
`0100`	PWM4 Trigger 1
`0011`	PWM3 Trigger 1
`0010`	PWM2 Trigger 1
`0001`	PWM1 Trigger 1
`0000`	`0`