8.6.3 Operations

The Reset status of Crypto module is controlled via the CAMCON register. The CAMCON SFR has the following module control bits: CAMON and CAMSIDL.

The CAMON bit enables operation of the module. If CAMON=0, the module is disabled, its internal state is reset and only the CAMCON register can be accessed. Additionally, the module can also be disabled using Peripheral Module Disable SFRs. Refer to Device Power-Saving Modes for more information.

Crypto SFR Access describes the module SFR access rights under each disable scenario.

Table 8-4. Crypto SFR Access
Crypto Module Implemented (Refer to Table 1 for details)	Crypto Module PMD bit PMD4[CRYMD]	CAMCON[CAMON]	ACCESS	ERROR
NO	0	0	NO	BMX Error⁽¹⁾
YES	-	-	Only the CAMCON register is accessible. Internal crypto registers are not acessible	Bus error when Crypto registers are accessed.
YES	0	1	Both CAMCON and Crypto registers are accessible.	No error
YES	1	1	Both CAMCON and Crypto registers are not accessible.	No error. The CAMCON and Crypto Module is held in Reset and reads 0.
Note: The BMX gives an error as unimplemented (invalid) space. BMXERR.ADDWERR or BMXERR.ADDRERR status bit gets set on trying to access Crypto registers when the module is not implemented in the device. Refer to Section 5.4 BMX Operation for more information.