8.6.3.4 Interrupts

The Crypto module provides three level sensitive interrupt signals to the interrupt controller, one each from symmetric, asymmetric crypto engines and TRNG.

Interrupt processing functions are included in the cryptographic firmware library.

• Integrated DMA of AES/HASH engine – _CRYPTO1Interrupt
  • The CRYPTO1Interrupt request is associated with the module’s integrated DMA transfer status. The engine raises an interrupt request upon completion of data transfer or on occurrence of any error response during the transaction.

• Asymmetric Crypto Engine – _CRYPTO2Interrupt
  • Asymmetric crypto engine raises the interrupt upon completion of instructed operation.

• TRNG – _CRYPTO3Interrupt
  • TRNG generates the interrupt request on any health test failure, FIFO read error or FIFO full status.

Additionally, these interrupts also need to be enabled within internal Crypto registers along with IEC bits for CPU to receive the interrupt request. Refer to Interrupt Controller for more details.

Any error in accessing the user RAM/Flash through Crypto module is logged onto the BMXCRYPT register. Note that such errors shall not raise any interrupts/traps, and user needs to monitor BMXCRYPT SFR at the end of each transaction.