26.5.7.4 CCPxPRL, CCPxRA and CCPxRB Write Status

In the operating modes, where the CCPxPRL, CCPxRA and CCPxRB are double-buffered, the PRLWIP (CCPxSTAT[20], RAWIP (CCPxSTAT[16]) and RBWIP (CCPxSTAT[17]) status bits indicate the buffer update status for these registers. The appropriate bit will set when one of these registers is written and will remain set until the buffered value takes effect, typically at the time-base period boundary.

Note: It is not necessary to monitor these three bits if software always updates the registers at a specific time in the time-base count period. This would occur, for example, when the time-base period interrupt is used to schedule an update in the software. If, however, software is expected to write these registers at a random time with respect to the time-base count period, then the appropriate status bit should be checked in software prior to performing the write.

Further writes to the CCPxPRL and/or CCPxRA/B registers should not be performed while the associated WIP status bit is set.