4.3.3 BMX Instruction RAM High Address Register

Name:	BMXIRAMH
Offset:	0x778


Bit	31	30	29	28	27	26	25	24
	BMXIRAMH[33:26]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	BMXIRAMH[25:18]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	BMXIRAMH[17:10]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	BMXIRAMH[9:4]
Access	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0

Bits 31:2 – BMXIRAMH[31:2] Upper Boundary Address for Instruction RAM bits

Defines the upper boundary address (non-inclusive) for instruction RAM.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.