4.3.1 Bus Initiator Priority Control Register

Note:
  1. CPU has the highest priority.
Name: BMXINITPR
Offset: 0x770

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
        ICDPR 
Access R/W 
Reset 0 
Bit 76543210 
 NVMPRCAN2PRCAN1PRCRYPTPRCPUPRYDATPRXDATPRDMAPR 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 8 – ICDPR ICD Priority Override bit

ValueDescription
1 Raise ICD initiator priority above CPU.
0 No change to ICD initiator priority

Bit 7 – NVMPR NVM Priority Override bit

ValueDescription
1 Raise NVM initiator RAM access priority above CPU.
0 No change to NVM initiator RAM access priority

Bit 6 – CAN2PR  CAN2 Priority Override bit

ValueDescription
1 Raise CAN 2 initiator priority above CPU.
0 No change to CAN 2 initiator priority

Bit 5 – CAN1PR  CAN1 Priority Override bit

ValueDescription
1 Raise CAN 1 initiator priority above CPU.
0 No change to CAN 1 initiator priority

Bit 4 – CRYPTPR  Crypto Priority Override bit

ValueDescription
1 Raise Crypto Accelerator priority above CPU.
0 No change to Crypto Accelerator priority

Bit 3 – CPUPR  CPU Priority Override bit

ValueDescription
1 Raise CPU initiator priority above CPU.
0 No change to CPU initiator priority

Bit 2 – YDATPR  Y RAM Priority Override bit

ValueDescription
1 Raise Y RAM initiator priority above CPU.
0 No change to Y RAM initiator priority

Bit 1 – XDATPR  X RAM Priority Override bit

ValueDescription
1 Raise X RAM initiator priority above CPU.
0 No change to X RAM initiator priority

Bit 0 – DMAPR DMA Priority Override bit

ValueDescription
1 Raise DMA initiator RAM access above CPU.
0 No change to DMA initiator RAM access priority