4.3.6 BMX Error Status Register for DMA Initiator
| Name: | BMXDMAERR |
| Offset: | 0x784 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DBGWERR | CRYPTWERR | YRAMWERR | XRAMWERR | SFRWERR | PGSPCWERR | ||||
| Access | R/HS/C | R/HS/C | R/HS/C | R/HS/C | R/HS/C | R/HS/C | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IRAMWERR | ADDWERR | BADTGTWERR | |||||||
| Access | R/HS/C | R/HS/C | R/HS/C | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DBGRERR | CRYPTRERR | YRAMRERR | XRAMRERR | SFRRERR | PGSPCRERR | ||||
| Access | R/HS/C | R/HS/C | R/HS/C | R/HS/C | R/HS/C | R/HS/C | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IRAMRDERR | ADDRERR | BADTGTRERR | |||||||
| Access | R/HS/C | R/HS/C | R/HS/C | ||||||
| Reset | 0 | 0 | 0 |
Bit 29 – DBGWERR Debug RAM Write Error bit
| Value | Description |
|---|---|
1 |
Bus error generated by debug RAM write operation. |
0 |
No error on debug RAM write operation |
Bit 28 – CRYPTWERR Crypto Write Error bit
| Value | Description |
|---|---|
1 |
Bus error generated by Crypto space write operation. |
0 |
No error on Crypto space write operation |
Bit 27 – YRAMWERR Y RAM Write Error bit
| Value | Description |
|---|---|
1 |
Bus error generated by Y RAM write operation. |
0 |
No error on Y RAM write operation |
Bit 26 – XRAMWERR X RAM Write Error bit
| Value | Description |
|---|---|
1 |
Bus error generated by X RAM write operation. |
0 |
No error on X RAM write operation |
Bit 25 – SFRWERR SFR Write Error bit
| Value | Description |
|---|---|
1 |
Bus error generated by SFR write operation. |
0 |
No error on SFR write operation |
Bit 24 – PGSPCWERR Program Space Write Error bit
| Value | Description |
|---|---|
1 |
Bus error generated by Program Space write operation. |
0 |
No error on Program Space write operation |
Bit 18 – IRAMWERR IRAM Write Error Flag bit
| Value | Description |
|---|---|
1 |
Error generated by invalid instruction write outside of IRAM space. |
0 |
No IRAM write address errors |
Bit 17 – ADDWERR Invalid Address Write Error Flag bit
| Value | Description |
|---|---|
1 |
Error generated by read or write to invalid address space. |
0 |
No unimplemented address write error |
Bit 16 – BADTGTWERR Invalid Target Write Error Flag bit
| Value | Description |
|---|---|
1 |
Error generated by write to disallowed target space. |
0 |
No invalid target write error |
Bit 13 – DBGRERR Debug RAM Read Error bit
| Value | Description |
|---|---|
1 |
Bus error generated by debug RAM read operation. |
0 |
No error on debug RAM read operation |
Bit 12 – CRYPTRERR Crypto Read Error bit
| Value | Description |
|---|---|
1 |
Bus error generated by Crypto space read operation. |
0 |
No error on Crypto space read operation |
Bit 11 – YRAMRERR Target y Bus Read Error Flag bit
| Value | Description |
|---|---|
1 |
Bus error generated by YRAM read operation. |
0 |
No error on YRAM read operation |
Bit 10 – XRAMRERR Target x Bus Read Error Flag bit
| Value | Description |
|---|---|
1 |
Bus error generated by XRAM read operation. |
0 |
No error on XRAM read operation |
Bit 9 – SFRRERR SFR Read Error bit
| Value | Description |
|---|---|
1 |
Bus error generated by the SFR read operation. |
0 |
No error on the SFR read operation |
Bit 8 – PGSPCRERR Program Space Read Error Flag bit
| Value | Description |
|---|---|
1 |
Bus error generated by program space read operation. |
0 |
No error on program space read operation |
Bit 2 – IRAMRDERR IRAM Read Error Flag bit
| Value | Description |
|---|---|
1 |
Error generated by invalid instruction read outside of IRAM space. |
0 |
No IRAM read address errors |
Bit 1 – ADDRERR Invalid Address Error Flag bit
| Value | Description |
|---|---|
1 |
Error generated by read or write to invalid address space. |
0 |
No unimplemented address write error |
Bit 0 – BADTGTRERR Invalid Target Read Error Flag bit
| Value | Description |
|---|---|
1 |
Error generated by read to disallowed target space. |
0 |
No invalid target error |