3.5.2.1 HPCCON Register
| Name: | HPCCON |
| Offset: | 0x1E10 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | CLR | ||||||||
| Access | R/W | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 15 – ON On Control bit
| Value | Description |
|---|---|
| 1 | Module is enabled and counters increment on event signals. |
| 0 | Module is disabled and counters do not increment on event signals. Counter values may be read. |
Bit 13 – CLR Clear Control bit
A write of a ‘1’ to this location will cause the event counters
to clear. This bit may be set at any time whether the PMU is in the Enabled
state or the Disabled state. This bit location always reads as
‘0’.