3.5.2.2 HPCSEL0 Register
| Name: | HPCSEL0 |
| Offset: | 0x1E10 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SELECT[3][4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SELECT[2][4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SELECT[1][4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SELECT[0][4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 28:24 – SELECT[3][4:0] Counter #3 Event Source Selection bits
These control bits determine which event is counted by the associated counter.
See Table 3-11 for assignments.
| Value | Description |
|---|---|
| 11111-00001 | Selects the event to be monitored. |
| 00000 | No event selected (1’b0); counter is disabled. |
Bits 20:16 – SELECT[2][4:0] Counter #2 Event Source Selection bits
These control bits determine which event is counted by the associated counter.
See Table 3-11 for assignments.
| Value | Description |
|---|---|
| 11111-00001 | Selects the event to be monitored. |
| 00000 | No event selected (1’b0); counter is disabled. |
Bits 12:8 – SELECT[1][4:0] Counter #1 Event Source Selection bits
These control bits determine which event is counted by the associated counter.
See Table 3-11 for assignments.
| Value | Description |
|---|---|
| 11111-00001 | Selects the event to be monitored. |
| 00000 | No event selected (1’b0); counter is disabled. |
Bits 4:0 – SELECT[0][4:0] Counter #0 Event Source Selection bits
These control bits determine which event is counted by the associated counter.
See Table 3-11 for assignments.
| Value | Description |
|---|---|
| 11111-00001 | Selects the event to be monitored. |
| 00000 | No event selected (1’b0); counter is disabled. |