Hardware Flow Control

Hardware flow control uses up to four additional pins to indicate when a device is ready to receive additional data. The four active-low device pins are shown in Table 20-6. Figure 20-10 shows connections between two UARTs.

Table 20-6. Hardware Flow Control Pin Functions
Signal NameDescriptionUsed ByDirection
UxDSRData-Set-ReadyTransmitterInput
UxRTSRequest-to-SendTransmitterOutput
UxCTSClear-to-SendReceiverInput
UxDTRData-Terminal-ReadyReceiverOutput
Figure 20-10. Hardware Flow Control Pins and Connections

The transmitter asserts (drives low) the UxRTS output when it has one or more bytes in its TX buffer to indicate that it wants to send a byte. Then, the transmitter listens to the UxDSR to see if it is OK to do so. If UxDSR is active (low), the transmitter sends one byte. If UxDSR is inactive (high), it will wait.

When the receiver detects the UxCTS signal going active (low), it checks to see if there are two empty slots in the receive buffer. If so, the receiver asserts (drives low) the UxDTR pin to indicate it is ready to receive data. No register setup is needed to enable the flow control pins. However, most devices will have the UART and associated flow control pins routed through the Peripheral Pin Select (PPS) feature.

When using flow control, devices can be categorized into two groups: DTE (Data Terminal Equipment) and DCE (Data Carrier Equipment). A typical DTE can be a computer or a microcontroller, and a DCE is typically a modem. Not all hardware flow control pins are needed in all cases. The following sections show which flow control pins are used to interface different devices to one another.