12.4.6.4 Setup for Using PLL with the Primary Oscillator (POSC)
The following process is used to set up the PLL to operate the device at 200 MHz with a 10 MHz external crystal:
- Set the configuration for the POSC to HS mode using POSCMD[1:0] bits in the OSCCFG register.
- Setting up divider settings: to execute
instructions at 200 MHz, a PLL output frequency of 200 MHz will be required. To set up
the PLL and meet the requirements of the PLL, follow these steps:
- Select the PLL prescaler.
- Select a PLL prescaler value of N1 = 1.
- FPLLI = 10 MHz
- FPFD = 10 MHz(1/N1) = 10 MHz(1) = 10 MHz
- Select the feedback divider to
meet the VCO output frequency requirement as well as achieve the desired
FVCO frequency.
- Select a feedback divider value of M = 100.
- FVCO = FPLLI x (M/N1) = 10 MHz x (100/1) = 1 GHz
- Select values for the first and
second PLL postscalers to achieve the required FPLLO frequency.
- Select values for the first and second postscalers of N2 = 5 and N3 = 1.
- FPLL FOUT/FPLLO = FVCO/(N2 x N3) = 1 GHz/5 = 200 MHz
- Enable the PLL Input and Feedback Divider update by setting the PLLSWEN bit in the PLLxCON register. Enable the PLL Output Divider update by setting the FOUTSWEN bit in the PLLxCON register.
- Select clock source by setting the NOSC[3:0] bits in the PLLxCON register to Primary (3).
- Enable clock switching by setting the OSWEN bit in the PLLxCON register.
- Select the PLL prescaler.
- Writing PLLxCON (can be done in one
PLLxCON write):
- Enable the PLL input and Feedback Divider update by setting the PLLSWEN bit in the PLLxCON register. Enable the PLL Output Divider update by setting the FOUTSWEN bit in the PLLxCON register.
- Select clock source by setting the NOSC[3:0] bits in the PLLxCON register to Primary (3).
- Enable clock switching by setting the OSWEN bit in the PLLxCON register.
Note: PLL1CON writes are written out for clarity, These
writes can be achieved in a single PLL1CON write.
Code Example for Using PLL with the Primary Oscillator (POSC)
// code example for 200 MHz PLL clock using 10 MHz crystal primary oscillator
//set crystal configuration using configuration register
OSCCFGbits.POSCMD = 2; //set desired Primary oscillator mode
// 0b00 : EC mode
// 0b10 : HS mode
// 0b01 : XT mode
// 0b11 : Disabled
//Enable PLL clock generator
PLL1CONbits.ON = 1;
PLL1CONbits.OE = 1;
//configure backup oscillator in case of failure
PLL1CONbits.BOSC = 2; //select BFRC backup clock source:
PLL1CONbits.FSCMEN = 1; //enable fail safe
//configure PLL values
PLL1DIVbits.PLLFBDIV = 100; //Feedback Divider
PLL1DIVbits.PLLPRE = 1; //Reference Clock Divider
PLL1DIVbits.POSTDIV1 = 5; //Post Divider #1
PLL1DIVbits.POSTDIV2 = 1; //Post Divider #2
// PLL Fout = Fin*FBDIV / (PLLPRE * POSTDIV1 * POSTDIV2)
// PLL Fout = 10M*100/(1*5*1) =200MHz
//Enable PLL Input and Feedback Divider update
PLL1CONbits.PLLSWEN = 1;
while (PLL1CONbits.PLLSWEN == 1);
//Enable PLL Output Divider update
PLL1CONbits.FOUTSWEN = 1;
while (PLL1CONbits.FOUTSWEN);
//select clock switching clock source
PLL1CONbits.NOSC = 3; //select POSC clock source
//[1] = FRC - Internal 8 MHz RC oscillator
//[2] = BFRC - Internal Backup 8 MHz RC oscillator
//[3] = POSC - Primary crystal oscillator (4-32 MHz)
//[9] = REFI1 - user definable clock source
//[10] = REFI2 - user definable clock source
PLL1CONbits.OSWEN = 1; //enable clock switching
while (PLL1CONbits.OSWEN); //wait for switching(hardware clear)
while(!OSCCTRLbits.PLL1RDY); //wait for clock to be ready