12.4.6.2 PLL Lock Status

Whenever the PLL input frequency, the PLL prescaler or the PLL feedback divider is changed, the PLL requires a finite amount of time (T_LOCK) to synchronize to the new settings.

T_LOCK is applied when the PLL is selected as the clock source during a clock switching operation. The value of T_LOCK is relative to the time at which the clock is available to the PLL input. For example, with the POSC, T_LOCK starts after the OST delay. For more information about oscillator start-up delay, see Oscillator Start-up Time. Also, refer to the Electrical Characteristics, Table 40-22, for more information about typical T_LOCK values.

The PLLxRDY bit in the Oscillator Control register (OSCCTRL[5]) and the CLKRDY bit in the PLL Control register PLLxCON[31] are read-only status bits that indicate the PLL ready status of the PLL. The LOCK bit is cleared at a Power-on Reset and on a clock switch operation when the PLL is selected as the destination clock source. It remains clear when any clock source not using the PLL is selected. After a clock switch event in which the PLL is enabled, it is advisable to wait for the LOCK bit to be set before executing other code.