28.3.12 PTG Step Queue 0 Pointer
Register
Legend: R = Readable bit, W = Writable bit
Note:
- These bits are read-only when
the module is executing step commands.
- Refer to Table 28-5 for the step command encoding.
| Name: | PTGQUE0 |
| Offset: | 0x3530 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | STEP3[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | STEP2[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | STEP1[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | STEP0[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:24 – STEP3[7:0]
PTG Command Step 3 bits(1,2)
A queue location for
storage of the STEP3 command byte.
Bits 23:16 – STEP2[7:0]
PTG Command Step 2 bits(1,2)
A queue location for storage
of the STEP2 command byte.
Bits 15:8 – STEP1[7:0]
PTG Command Step 1 bits(1,2)
A queue location for storage
of the STEP1 command byte.
Bits 7:0 – STEP0[7:0]
PTG Command Step 0 bits(1,2)
A queue location for storage
of the STEP0 command byte.
