25.4.10 Writing to TxCON, TMRx and PRx Registers

The Timer module is disabled and powered off when the TON bit (TxCON[15]) = 0, thus providing maximum power savings.

The timer register can be written while the module is operating. The bus write always has priority over the timer increment.

If 0xFFFFFFFF is written into the timer register, the next timer count clock after this write will cause the timer to roll over to 0x00000000.

To prevent unpredictable timer behavior, it is recommended that the timer be disabled before writing to any of the TxCON register bits or the timer input clock prescaler. Attempting to set the TON bit = 1 and writing to any TxCON register bits in the same instruction may cause an erroneous timer operation.

The PRx Period register can be written to while the module is operating. However, to prevent unintended period matches, writing to the PRx Period register while the timer is enabled (TON bit = 1) is not recommended.

The user must write the TxCON register to establish the operating mode prior to any updates to the TMRx register. The user is allowed to write the TMRx register while the timer is running. Writes to TMRx while the timer is running require the following synchronization sequence to be completed:

• Three timer domain clocks: two to sync the written data and TMRWIP bit and one to perform the

write into TMRx.

• An additional two system clocks after the write completes are needed to sync TMRx to the system domain

If the user attempts to write the timer again while the current write is awaiting synchronization, the value written to the timer can be corrupted.

The TMRx Count register is not reset to zero when the module is disabled.

For read write operation on timer in external asynchronous mode refer to Asynchronous Clock Counter Mode.

Two bits in the TxCON register can be used to ensure that writes during timer operation will not cause the timer value to be corrupted. The TxCON.TMWDIS bit, when set, will prevent a write to the timer and period registers when a previous write to the timer is awaiting synchronization into the asynchronous timer clock domain. The TxCON.TMWIP bit indicates when write synchronization is complete and it is safe to write another value to the timer.

In Asynchronous mode, writes are synchronized once the high byte is written, at which point the TxCON.PRWIP bit is set.

The TxCON.TMWDIS bit, when set, will prevent a write to the timer or period registers when a previous write to that register is awaiting synchronization into the asynchronous timer clock domain. The TxCON.TMWIP and TxCON.PRWIP bits indicate when write synchronization is complete and it is safe to write another value to the timer.

In synchronous mode, writes have immediate effect upon write to registers PRx and TMRx. TxCON Status bits (TMWIP & PRWIP) will not update in synchronous mode. The TxCON.TMWDIS bit has no effect in synchronous mode.

Note: If a write to TMR is completed (and TMWIP cleared) on the same cycle where TMR = PR, an interrupt will still be generated and the timer will still read as ‘0’ on the subsequent cycle due to the timing of the synchronization logic. Customer code that writes to the asynchronous timer while it is running should be capable of ignoring the unintended interrupt if necessary.