25.4.2 Synchronous External Clock Counter Mode

When TxCON.TCS = 1, TxCON.TON = 1 and TxCON.TSYNC = 1, the timer increments on the synchronized rising edge of the applied external clock signal. The synchronization of the input signal occurs with the internal system clock signal. The timer counts up to a match value preloaded in the period register, then resets and continues. This incrementing sequence repeats until the timer is disabled (refer to Figure 25-3).

Figure 25-3. Synchronized External Clock Mode Timing Diagram

When the CPU goes into Sleep mode, or when the timer is configured for the Synchronous mode of operation and the CPU goes into Idle mode with TxCON.SIDL = 1, the timer will stop incrementing.

The timer module logic will resume the incrementing sequence upon termination of the CPU Idle/Sleep mode. If TxCON.SIDL = 0, the timer will continue to operate.