Status

Name:
STATUS
Offset:
0x01
Reset:
0x00
Access:
Configuration Change Protection
 Bit7 6 5 4 3 2 1 0 LOCK SYNCBUSY AccessR/W R Reset0 0

## Bit 7 – LOCK: Lock

Lock

Writing this bit to ‘1’ write-protects the WDT.CTRLA register.

It is only possible to write this bit to ‘1’. This bit can be cleared in Debug mode only.

If the PERIOD value in the WDTCFG fuse is different from zero, the lock will be automatically set.

This bit is under CCP.

## Bit 0 – SYNCBUSY: Synchronization Busy

Synchronization Busy

This bit is set after writing to the WDT.CTRLA register, while the data is being synchronized from the peripheral clock domain to the WDT clock domain.

This bit is cleared after finishing the synchronization.

This bit is not under CCP.