Interrupt Flag Register - Split Mode

Name:
INTFLAGS
Offset:
0x0B
Reset:
0x00
Access:
-
Bit76543210
LCMP2LCMP1LCMP0HUNFLUNF
AccessR/WR/WR/WR/WR/W
Reset00000

Bit 6 – LCMP2: Low byte Compare Channel 2 Interrupt Flag

Low byte Compare Channel 2 Interrupt Flag

See LCMP0 flag description.

Bit 5 – LCMP1: Low byte Compare Channel 1 Interrupt Flag

Low byte Compare Channel 1 Interrupt Flag

See LCMP0 flag description.

Bit 4 – LCMP0: Low byte Compare Channel 0 Interrupt Flag

Low byte Compare Channel 0 Interrupt Flag

The Low byte Compare Interrupt (LCMPn) flag is set on a compare match on the corresponding compare channel in the low byte timer.

For all modes of operation, the LCMPn flag will be set when a compare match occurs between the Low Byte Timer Counter (TCAn.LCNT) register and the corresponding Compare n (TCAn.LCMPn) register. Software must clear the LCMPn flag as it will not be cleared automatically. Writing a ‘1’ to its bit location will do this.

Bit 1 – HUNF: High byte Underflow Interrupt Flag

High byte Underflow Interrupt Flag

This flag is set on a high byte timer BOTTOM (underflow) condition. HUNF is not automatically cleared and needs to be cleared by software. Writing a ‘1’ to its bit location will do this.

Bit 0 – LUNF: Low byte Underflow Interrupt Flag

Low byte Underflow Interrupt Flag

This flag is set on a low byte timer BOTTOM (underflow) condition. LUNF is not automatically cleared and needs to be cleared by software. Writing a ‘1’ to its bit location will do this.