Control A

Name:
CTRLA
Offset:
0x00
Reset:
0x00
Access:
Enable-protected
Bit76543210
CLKSEL[1:0]CNTPRES[1:0]SYNCPRES[1:0]ENABLE
AccessR/WR/WR/WR/WR/WR/WR/W
Reset0000000

Bits 6:5 – CLKSEL[1:0]: Clock Select

Clock Select

The Clock Select bit field selects the clock source of the TCD clock.

Value Name Description
0x0 OSCHF Internal high-frequency oscillator
0x1 PLL PLL
0x2 EXTCLK External clock
0x3 SYSCLK System clock

Bits 4:3 – CNTPRES[1:0]: Counter Prescaler

Counter Prescaler

The Counter Prescaler bit field selects the division factor of the TCD counter clock.

ValueNameDescription
0x0 DIV1 Division factor 1
0x1 DIV4 Division factor 4
0x2 DIV32 Division factor 32
0x3 - Reserved

Bits 2:1 – SYNCPRES[1:0]: Synchronization Prescaler

Synchronization Prescaler

The Synchronization Prescaler bit field selects the division factor of the TCD clock.

ValueNameDescription
0x0 DIV1 Division factor 1
0x1 DIV2 Division factor 2
0x2 DIV4 Division factor 4
0x3 DIV8 Division factor 8

Bit 0 – ENABLE: Enable

Enable

When writing to this bit, it will automatically be synchronized to the TCD clock domain.

This bit can be changed as long as the synchronization of this bit is not ongoing. See the Enable Ready (ENRDY) bit in the Status (TCDn.STATUS) register.

This bit is not enable-protected.

ValueNameDescription
0 NO The TCD is disabled
1 YES The TCD is enabled and running