38.7.23 Device Endpoint Interrupt Disable Register (Control, Bulk, Interrupt Endpoints)

This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.

For additional information, see ”Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding bit in USBHS_DEVEPTIMRx.

Name:	USBHS_DEVEPTIDRx
Offset:	0x0220 + x*0x04 [x=0..8]
Reset:	0
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					STALLRQC		NYETDISC	EPDISHDMAC
Access					R/W		R/W	R/W
Reset					0		0	0


Bit	15	14	13	12	11	10	9	8
		FIFOCONC		NBUSYBKEC
Access		R/W		R/W
Reset		0		0


Bit	7	6	5	4	3	2	1	0
	SHORTPACKETEC	STALLEDEC	OVERFEC	NAKINEC	NAKOUTEC	RXSTPEC	RXOUTEC	TXINEC
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 19 – STALLRQC STALL Request Clear

Bit 17 – NYETDISC NYET Token Disable Clear

Bit 16 – EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear

Bit 14 – FIFOCONC FIFO Control Clear

Bit 12 – NBUSYBKEC Number of Busy Banks Interrupt Clear

Bit 7 – SHORTPACKETEC Shortpacket Interrupt Clear

Bit 6 – STALLEDEC STALLed Interrupt Clear

Bit 5 – OVERFEC Overflow Interrupt Clear

Bit 4 – NAKINEC NAKed IN Interrupt Clear

Bit 3 – NAKOUTEC NAKed OUT Interrupt Clear

Bit 2 – RXSTPEC Received SETUP Interrupt Clear

Bit 1 – RXOUTEC Received OUT Data Interrupt Clear

Bit 0 – TXINEC Transmitted IN Interrupt Clear

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