The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_DEVISR.
Name:
USBHS_DEVIFR
Offset:
0x000C
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
DMA_6
DMA_5
DMA_4
DMA_3
DMA_2
DMA_1
DMA_0
Access
W
W
W
W
W
W
W
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
UPRSMS
EORSMS
WAKEUPS
EORSTS
SOFS
MSOFS
SUSPS
Access
W
W
W
W
W
W
W
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Set
Bit 6 – UPRSMS Upstream Resume Interrupt Set
Bit 5 – EORSMS End of Resume Interrupt Set
Bit 4 – WAKEUPS Wakeup Interrupt Set
Bit 3 – EORSTS End of Reset Interrupt Set
Bit 2 – SOFS Start of Frame Interrupt Set
Bit 1 – MSOFS Micro Start of Frame Interrupt Set
Bit 0 – SUSPS Suspend Interrupt Set
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
