38.7.29 Device DMA Channel x Control Register
| Name: | USBHS_DEVDMACONTROLx |
| Offset: | 0x0308 + (x-1)*0x10 [x=1..7] |
| Reset: | 0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BUFF_LENGTH[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BUFF_LENGTH[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:16 – BUFF_LENGTH[15:0] Buffer Byte Length (Write-only)
This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (32 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the transfer end may occur earlier under USB device control.
When this field is written, the USBHS_DEVDMASTATUSx.BUFF_COUNT field is updated with the write value.
Bit 7 – BURST_LCK Burst Lock Enable
| Value | Description |
|---|---|
| 0 | The DMA never locks bus access. |
| 1 | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. |
Bit 6 – DESC_LD_IT Descriptor Loaded Interrupt Enable
| Value | Description |
|---|---|
| 0 | USBHS_DEVDMASTATUSx.DESC_LDST rising does not trigger any interrupt. |
| 1 | An interrupt is generated when a descriptor has been loaded from the bus. |
Bit 5 – END_BUFFIT End of Buffer Interrupt Enable
| Value | Description |
|---|---|
| 0 | USBHS_DEVDMA_STATUSx.END_BF_ST rising does not trigger any interrupt. |
| 1 | An interrupt is generated when USBHS_HSTDMASTATUSx.BUFF_COUNT reaches zero. |
Bit 4 – END_TR_IT End of Transfer Interrupt Enable
Use when the receive size is unknown.
| Value | Description |
|---|---|
| 0 | USBHS device-initiated buffer transfer completion does not trigger any interrupt at USBHS_DEVDMASTATUSx.END_TR_ST rising. |
| 1 | An interrupt is sent after the buffer transfer is complete, if the USBHS device has ended the buffer transfer. |
Bit 3 – END_B_EN End of Buffer Enable Control
This is mainly for short packet IN validations initiated by the DMA reaching end of buffer, but can be used for OUT packet truncation (discarding of unwanted packet data) at the end of DMA buffer.
| Value | Description |
|---|---|
| 0 | DMA Buffer End has no impact on USB packet transfer. |
| 1 | The endpoint can validate the packet (according to the values programmed in the USBHS_DEVEPTCFGx.AUTOSW and USBHS_DEVEPTIERx.SHORTPACKETES fields) at DMA Buffer End, i.e., when USBHS_DEVDMASTATUS.BUFF_COUNT reaches 0. |
Bit 2 – END_TR_EN End of Transfer Enable Control (OUT transfers only)
When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) closes the current buffer and the USBHS_DEVDMASTATUSx.END_TR_ST flag is raised.
This is intended for a USBHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure.
| Value | Description |
|---|---|
| 0 | The USB end of transfer is ignored. |
| 1 | The USBHS device can put an end to the current buffer transfer. |
Bit 1 – LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command
If the CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request.
DMA Channel Control Command Summary:
| Value LDNXT_DSC | Value CHANN_ENB | Name | Description |
| 0 | 0 | STOP_NOW | Stop now |
| 0 | 1 | RUN_AND_STOP | Run and stop at end of buffer |
| 1 | 0 | LOAD_NEXT_DESC | Load next descriptor now |
| 1 | 1 | RUN_AND_LINK | Run and link at end of buffer |
| Value | Description |
|---|---|
| 0 | No channel register is loaded after the end of the channel transfer. |
| 1 | The channel controller loads the next descriptor after the end of the current transfer, i.e., when the USBHS_DEVDMASTATUS.CHANN_ENB bit is reset. |
Bit 0 – CHANN_ENB Channel Enable Command
| Value | Description |
|---|---|
| 0 | The DMA channel is disabled at end of transfer and no transfer occurs upon request. This bit is also cleared by hardware when the channel source bus is disabled at end of buffer. If the LDNXT_DSC bit has been cleared by descriptor loading, the firmware must set the corresponding CHANN_ENB bit to start the described transfer, if needed. If the LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both USBHS_DEVDMASTATUS.CHANN_ENB and CHANN_ACT flags read as 0. If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the USBHS_DEVDMASTATUS.CHANN_ENB bit is cleared. If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded. |
| 1 | The USBHS_DEVDMASTATUS.CHANN_ENB bit is set, thus enabling the DMA channel data transfer. Then, any pending request starts the transfer. This may be used to start or resume any requested transfer. |