38.7.5 Device General Control Register
| Name: | USBHS_DEVCTRL |
| Offset: | 0x0000 |
| Reset: | 0x00000100 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OPMODE2 | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TSTPCKT | TSTK | TSTJ | LS | SPDCONF[1:0] | RMWKUP | DETACH | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADDEN | UADD[6:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 16 – OPMODE2 Specific Operational mode
| Value | Description |
|---|---|
| 0 | The UTMI transceiver is in Normal operating mode. |
| 1 | The UTMI transceiver is in the “Disable bit stuffing and NRZI encoding” operational mode for test purposes. |
Bit 15 – TSTPCKT Test packet mode
| Value | Description |
|---|---|
| 0 | The UTMI transceiver is in Normal operating mode. |
| 1 | The UTMI transceiver generates test packets for test purposes. |
Bit 14 – TSTK Test mode K
| Value | Description |
|---|---|
| 0 | The UTMI transceiver is in Normal operating mode. |
| 1 | The UTMI transceiver generates high-speed K state for test purposes. |
Bit 13 – TSTJ Test mode J
| Value | Description |
|---|---|
| 0 | The UTMI transceiver is in Normal operating mode. |
| 1 | The UTMI transceiver generates high-speed J state for test purposes. |
Bit 12 – LS Low-Speed Mode Force
This bit can be written even if USBHS_CTRL.USBE = 0 or USBHS_CTRL.FRZCLK = 1. Disabling the USBHS (by writing a zero to the USBHS_CTRL.USBE bit) does not reset this bit.
| Value | Description |
|---|---|
| 0 | The Full-speed mode is active. |
| 1 | The Low-speed mode is active. |
Bits 11:10 – SPDCONF[1:0] Mode Configuration
This field contains the peripheral speed:
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. |
| 1 | LOW_POWER | For a better consumption, if high speed is not needed. |
| 2 | HIGH_SPEED | Forced high speed. |
| 3 | FORCED_FS | The peripheral remains in Full-speed mode whatever the host speed capability. |
Bit 9 – RMWKUP Remote Wakeup
This bit is cleared when the USBHS receives a USB reset or once the upstream resume has been sent.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Sends an upstream resume to the host for a remote wakeup. |
Bit 8 – DETACH Detach
| Value | Description |
|---|---|
| 0 | Reconnects the device. |
| 1 | Physically detaches the device (disconnects the internal pull-up resistor from D+ and D-). |
Bit 7 – ADDEN Address Enable
This bit is cleared when a USB reset is received.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Activates the UADD field (USB address). |
Bits 6:0 – UADD[6:0] USB Address
This field contains the device address.
This field is cleared when a USB reset is received.