38.7.51 Host Pipe x Set Register (Control, Bulk Pipes)

This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.

For additional information, see ”Host Pipe x Status Register (Control, Bulk Pipes)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Sets the corresponding bit in USBHS_HSTPIPISRx, which may be useful for test or debug purposes.

Name: USBHS_HSTPIPIFRx
Offset: 0x0590
Reset: 0
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
    NBUSYBKS     
Access R/W 
Reset 0 
Bit 76543210 
 SHORTPACKETISRXSTALLDISOVERFISNAKEDISPERRISTXSTPISTXOUTISRXINIS 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 12 – NBUSYBKS Number of Busy Banks Set

Bit 7 – SHORTPACKETIS Short Packet Interrupt Set

Bit 6 – RXSTALLDIS Received STALLed Interrupt Set

Bit 5 – OVERFIS Overflow Interrupt Set

Bit 4 – NAKEDIS NAKed Interrupt Set

Bit 3 – PERRIS Pipe Error Interrupt Set

Bit 2 – TXSTPIS Transmitted SETUP Interrupt Set

Bit 1 – TXOUTIS Transmitted OUT Data Interrupt Set

Bit 0 – RXINIS Received IN Data Interrupt Set