38.7.24 Device Endpoint Interrupt Disable Register (Isochronous Endpoints)
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVEPTIMRx.
| Name: | USBHS_DEVEPTIDRx (ISOENPT) |
| Offset: | 0x0220 + x*0x04 [x=0..8] |
| Reset: | 0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EPDISHDMAC | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIFOCONC | NBUSYBKEC | ERRORTRANSEC | DATAXEC | MDATEC | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHORTPACKETEC | CRCERREC | OVERFEC | HBISOFLUSHEC | HBISOINERREC | UNDERFEC | RXOUTEC | TXINEC | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |