38.7.68 Host DMA Channel x Status Register
| Name: | USBHS_HSTDMASTATUSx |
| Offset: | 0x070C + x*0x10 [x=0..6] |
| Reset: | 0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BUFF_COUNT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BUFF_COUNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DESC_LDST | END_BF_ST | END_TR_ST | CHANN_ACT | CHANN_ENB | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bits 31:16 – BUFF_COUNT[15:0] Buffer Byte Count
This field determines the current number of bytes still to be transferred for this buffer.
This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word boundary.
At the end of buffer, the DMA accesses the USBHS device only for the number of bytes needed to complete it.
Note: For IN pipes, if the receive buffer byte length (USBHS_HSTDMACONTROL.BUFF_LENGTH) has been defaulted to zero because the USB transfer length is unknown, the actual buffer byte length received is 0x10000-BUFF_COUNT.
Bit 6 – DESC_LDST Descriptor Loaded Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
| Value | Description |
|---|---|
| 0 | Cleared automatically when read by software. |
| 1 | Set by hardware when a descriptor has been loaded from the system bus. |
Bit 5 – END_BF_ST End of Channel Buffer Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
| Value | Description |
|---|---|
| 0 | Cleared automatically when read by software. |
| 1 | Set by hardware when the BUFF_COUNT count-down reaches zero. |
Bit 4 – END_TR_ST End of Channel Transfer Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
| Value | Description |
|---|---|
| 0 | Cleared automatically when read by software. |
| 1 | Set by hardware when the last packet transfer is complete, if the USBHS device has ended the transfer. |
Bit 1 – CHANN_ACT Channel Active Status
When a packet transfer is ended, this bit is automatically reset.
When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if any) and potentially until completion of a USBHS packet transfer, if allowed by the new descriptor.
| Value | Description |
|---|---|
| 0 | The DMA channel is no longer trying to source the packet data. |
| 1 | The DMA channel is currently trying to source packet data, i.e., selected as the highest-priority requesting channel. |
Bit 0 – CHANN_ENB Channel Enable Status
When any transfer is ended either due to an elapsed byte count or to completion of a USBHS device-initiated transfer, this bit is automatically reset.
This bit is normally set or cleared by writing into the USBHS_HSTDMACONTROLx.CHANN_ENB bit field either by software or descriptor loading.
If a channel request is currently serviced when the USBHS_HSTDMACONTROLx.CHANN_ENB bit is cleared, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
| Value | Description |
|---|---|
| 0 | If cleared, the DMA channel no longer transfers data, and may load the next descriptor if the USBHS_HSTDMACONTROLx.LDNXT_DSC bit is set. |
| 1 | If set, the DMA channel is currently enabled and transfers data upon request. |