38.7.35 Host Global Interrupt Mask Register
| Name: | USBHS_HSTIMR |
| Offset: | 0x0410 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | DMA_0 | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PEP_9 | PEP_8 | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PEP_7 | PEP_6 | PEP_5 | PEP_4 | PEP_3 | PEP_2 | PEP_1 | PEP_0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HWUPIE | HSOFIE | RXRSMIE | RSMEDIE | RSTIE | DDISCIE | DCONNIE | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Enable
| Value | Description |
|---|---|
| 0 | Cleared when the corresponding bit in USBHS_HSTIDR = 1. This disables the DMA Channel x Interrupt (USBHS_HSTISR.DMA_x). |
| 1 | Set when the corresponding bit in USBHS_HSTIER = 1. This enables the DMA Channel x Interrupt (USBHS_HSTISR.DMA_x). |
Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 – PEP_ Pipe x Interrupt Enable
| Value | Description |
|---|---|
| 0 | Cleared when PEP_x = 1. This disables the Pipe x Interrupt (PEP_x). |
| 1 | Set when the corresponding bit in USBHS_HSTIER = 1. This enables the Pipe x Interrupt (USBHS_HSTISR.PEP_x). |
Bit 6 – HWUPIE Host Wakeup Interrupt Enable
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTIDR.HWUPIEC = 1. This disables the Host Wakeup Interrupt (USBHS_HSTISR.HWUPI). |
| 1 | Set when USBHS_HSTIER.HWUPIES = 1. This enables the Host Wakeup Interrupt (USBHS_HSTISR.HWUPI). |
Bit 5 – HSOFIE Host Start of Frame Interrupt Enable
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTIDR.HSOFIEC = 1. This disables the Host Start of Frame interrupt (USBHS_HSTISR.HSOFI). |
| 1 | Set when USBHS_HSTIER.HSOFIES= 1. This enables the Host Start of Frame interrupt (USBHS_HSTISR.HSOFI). |
Bit 4 – RXRSMIE Upstream Resume Received Interrupt Enable
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTIDR.RXRSMIEC= 1. This disables the Downstream Resume interrupt (USBHS_HSTISR.RXRSMI). |
| 1 | Set when USBHS_HSTIER.RXRSMIES = 1. This enables the Upstream Resume Received interrupt (USBHS_HSTISR.RXRSMI). |
Bit 3 – RSMEDIE Downstream Resume Sent Interrupt Enable
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTIDR.RSMEDIEC = 1. This disables the Downstream Resume interrupt (USBHS_HSTISR.RSMEDI). |
| 1 | Set when USBHS_HSTIER.RSMEDIES = 1. This enables the Downstream Resume interrupt (USBHS_HSTISR.RSMEDI). |
Bit 2 – RSTIE USB Reset Sent Interrupt Enable
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTIDR.RSTIEC = 1. This disables the USB Reset Sent interrupt (USBHS_HSTISR.RSTI). |
| 1 | Set when USBHS_HSTIER.RSTIES = 1. This enables the USB Reset Sent interrupt (USBHS_HSTISR.RSTI). |
Bit 1 – DDISCIE Device Disconnection Interrupt Enable
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTIDR.DDISCIEC = 1. This disables the Device Disconnection interrupt (USBHS_HSTISR.DDISCI). |
| 1 | Set when USBHS_HSTIER.DDISCIES = 1. This enables the Device Disconnection interrupt (USBHS_HSTISR.DDISCI). |
Bit 0 – DCONNIE Device Connection Interrupt Enable
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTIDR.DCONNIEC = 1. This disables the Device Connection interrupt (USBHS_HSTISR.DCONNI). |
| 1 | Set when USBHS_HSTIER.DCONNIES = 1. This enables the Device Connection interrupt (USBHS_HSTISR.DCONNI). |