38.7.37 Host Global Interrupt Enable Register

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Sets the corresponding bit in USBHS_HSTISR.

Name:	USBHS_HSTIER
Offset:	0x0418
Property:	Write-only


Bit	31	30	29	28	27	26	25	24
	DMA_6	DMA_5	DMA_4	DMA_3	DMA_2	DMA_1	DMA_0
Access	W	W	W	W	W	W	W
Reset


Bit	23	22	21	20	19	18	17	16
							PEP_9	PEP_8
Access							W	W
Reset


Bit	15	14	13	12	11	10	9	8
	PEP_7	PEP_6	PEP_5	PEP_4	PEP_3	PEP_2	PEP_1	PEP_0
Access	W	W	W	W	W	W	W	W
Reset


Bit	7	6	5	4	3	2	1	0
		HWUPIES	HSOFIES	RXRSMIES	RSMEDIES	RSTIES	DDISCIES	DCONNIES
Access		W	W	W	W	W	W	W
Reset

Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Enable

Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 – PEP_ Pipe x Interrupt Enable

Bit 6 – HWUPIES Host Wakeup Interrupt Enable

Bit 5 – HSOFIES Host Start of Frame Interrupt Enable

Bit 4 – RXRSMIES Upstream Resume Received Interrupt Enable

Bit 3 – RSMEDIES Downstream Resume Sent Interrupt Enable

Bit 2 – RSTIES USB Reset Sent Interrupt Enable

Bit 1 – DDISCIES Device Disconnection Interrupt Enable

Bit 0 – DCONNIES Device Connection Interrupt Enable

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