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38.7.9 Device Global Interrupt Mask Register The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name: USBHS_DEVIMR Offset: 0x0010 Reset: 0x00000000 Property: Read-only
Bit 31 30 29 28 27 26 25 24 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 DMA_0 Access R R R R R R R Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 PEP_9 PEP_8 PEP_7 PEP_6 PEP_5 PEP_4 Access R R R R R R Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 PEP_3 PEP_2 PEP_1 PEP_0 Access R R R R Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0 UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE Access R R R R R R R Reset 0 0 0 0 0 0 0
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Mask
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PEP_ Endpoint x Interrupt Mask
Bit 6 – UPRSME Upstream Resume Interrupt Mask
Bit 5 – EORSME End of Resume Interrupt Mask
Bit 4 – WAKEUPE Wakeup Interrupt Mask
Bit 3 – EORSTE End of Reset Interrupt Mask
Bit 2 – SOFE Start of Frame Interrupt Mask
Bit 1 – MSOFE Micro Start of Frame Interrupt Mask
Bit 0 – SUSPE Suspend Interrupt Mask
On this page
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Mask Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PEP_ Endpoint x Interrupt Mask Bit 6 – UPRSME Upstream Resume Interrupt Mask Bit 5 – EORSME End of Resume Interrupt Mask Bit 4 – WAKEUPE Wakeup Interrupt Mask Bit 3 – EORSTE End of Reset Interrupt Mask Bit 2 – SOFE Start of Frame Interrupt Mask Bit 1 – MSOFE Micro Start of Frame Interrupt Mask Bit 0 – SUSPE Suspend Interrupt Mask
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